![]() There are many applications that benefit from small TSV sizes. In contrast, fine-grain 3D technologies are defined as those having TSV pitches smaller than 500nm. When you start comparing these with on-chip feature sizes (28nm), you'll understand why I use the term "huge" to describe these TSVs. Other manufacturers are offering similar TSV sizes too. For example, TSMC's 28nm technology has 6um diameter TSVs with 5um keep-out zone. Now, let me describe the stuff I presented there.Īs many of you know, 3D technologies in the marketplace today have huge TSVs. Check out their website if you get a chance - they have some nice talks lined up for the future. In case you're not familiar with this IEEE chapter, they host speakers from around the Valley periodically. The Silicon Valley IEEE Components, Packaging and Manufacturing Technology (CPMT) Society invited me to give a talk on "Fine-Grain 3D Integration" last week. Evolutionary advances with today's TSV technology as well as radically new monolithic 3D approaches are options. CMOS integratedĬircuits are fabricated on thin circular slices of silicon called wafers.Today, we'll discuss why TSV pitches smaller than 500nm are useful and how one can achieve that. This chapter discusses the CMOS IC technology in details. This rapid increase is made possible by continuing The number of transistors on an IC chip increasing more rapidly doublingĮvery 18-24 months. Because of the combination of smaller feature size Rapid decrease in minimum feature size, the size of the IC chipĬontinuously increasing. The minimum feature size on an integrated circuit has continued to evolveĪt a rapid rate decreasing from 8 mm in 1969 to 90 nm today. The most important steps in the planar process are shown in Figure.TheĬ) Deposition of dopant atoms on or near the wafer surface.ĭ) Diffusion of dopant atoms into exposed silicon regions. Through a sequence of steps carried out near the surface plane of the Planar process because it is a process that produces device structures Major breakthrough to the IC fabrication technology. ![]() This process is called as the silicon planar process which gives a Proper sequencing and repetition of the oxidation, patterning and dopantĪddition operations, p and n dopant atoms are introduced into selective Placed in chamber that deposits dopant atoms on the surface then the dopantĪtoms enter the silicon only at the exposed silicon windows. For lithographic printingĪpplications which forms a very small patterns. Selective etching process originally developed. Surface consisting of base silicon windows in silicon dioxide layer. Hydrofluoric acid bath or exposed to gas phase etchants, this forms a Selected oxide regions on the silicon surface when it is immersed in Polymer films exposed with photographic masks. ![]() The shielded regions can be accurately defined by using photosensitive Using theseįeatures dopant atoms can be introduced into areas on the silicon that are Is silicon dioxide can be used to shield on underlying silicon crystal fromĭopant impurity atoms brought to the surface either by high energy ionīeams or from a high temperature gaseous diffusion source. Selective etching is possible using liquid or gaseous etchants and second Two chemical properties of Si-SiO 2 system are of basic importance to silicon technology. Workhorse for IC technology because of its ability to form a stable andĬontrollable silicon dioxide layer. Of diode and the invention of the transistor in late 1940s at that time Technological evolutions toward integrated circuits began with development
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